Jiashan Fudan Institute is approved by the Jiashan County Board editorial Board approval of the business unit of a legal person, by the Jiashan County people's government authorized Jiashan County Economic and Technological Development Zone Management Committee as organized units, Fudan University cooperation in Co-construction, construction purposes around the local industrial development needs, through scientific and technological innovation, the promotion of local economic development, serving the local industrial upgrading. Business scope includes integrated circuits, electronic communications, big data, health and other fields of basic research, the core technology R & D, innovation, talent cultivation, scientific and technological achievements transformation, industry incubation and promotion, management consulting and technical services.
Institute of relying on the Fudan University and the National Integrated Circuit Innovation Center in the field of integrated circuits of the core advantages, fully absorbed in the Yangtze River Delta integrated circuit original strengths, guide Shanghai and China, the global integrated circuit-related scientific research in Zhejiang achieve the transformation, the promotion of Zhejiang province Integrated Circuit Industry Transformation and upgrading, accelerate the development and build a first-class integrated circuit cluster for the Yangtze River Delta of the Integrated Circuit Industry Development to explore new paths, the accumulation of new experiences.
The Institute is located in Jiashan County Economic Development Zone of the Yangtze River Delta integration demonstration zone, currently has Xiangfu swing kechuang Green Valley 5300 square meters of office area, mainly used for chip design and testing, integrated circuits, talent training and other functions; with Xinda industrial Park of nearly 10,000 square meters of the plant, containing one hundred and one thousand, ten thousand grade clean room, can meet the integrated process development and product test requirements.
1. Responsible for the module, the top layer from Netlist to GDSII the whole process of implementation;
2. Is responsible for the appropriate floorplan, and a discussion is given of the pin assignment adjustment recommendations;
3. Responsible for the module level, the top of the APR work;
4. Responsible for timing closure, power analysis and optimization;
5. Complete the tapeout process: in-house and third-party IP merge, PV, including DRC&LVS&Antenna check to ensure that the chip successful tapeout;
6. After the completion of the end of the PI simulation analysis, and adjust accordingly.
1. A Chip-level Floorplan/Placement/CTS/Routing/PV and other aspects of the experience;
2. A low-power design experience, IR drop analysis, according to the power analysis of the amended design, familiar with UPF/CPF; and
3. Manually modify the DRC/LVS/ERC/Antanna; and
4. Proficiency in the use of mainstream chip digital design tools, such as DC,ICC/ICC2, EDI/INNOVUS, PT, Calibre, learn how;
5. Be proficient in the use Tcl, Perl, Python and other scripting build automated processes;
6. A high-speed radio frequency, high-speed ADC interface circuit and the calibration Circuit of back-end implementation experience;
7. Successful tape out of the experience.