Company description

Beijing Yi de Wei Computing Technology Co., Ltd. （hereinafter referred to as“Yi de Wei computing”is a RISC-V CPU as the core of next-generation computing architecture chip and solution providers around the smart home, intelligent campus, intelligent transportation, wireless communication, industrial IOT applications such as scene, providing customers with multimedia systems, interactive display, wisdom, connection, power management, intelligent computing, automotive systems and other chip solutions, promote the AIoT era of cloud-network integration of the hash rate of the network development.

Yi de Wei computing in 2019 began to force the RISC-V computing architecture independent research and development, has completed a series of 32-bit kernel processor developed, and applied to the dozens of self-developed chip product; and a 64-bit kernel high-performance processors opening flow sheet, The Associated chip product will be used for multimedia, edge computing, wearable devices, and General purpose computing and other scenes.

Yi de Wei calculate the global semiconductor industry experienced technical R & D and management team, headquartered in Beijing, in Beijing, XI'an, Haining, Hefei, Chengdu, Shanghai, Nanjing, Shenzhen, Changsha, Suzhou, UK, South Korea, and has R & D centers in Beijing, Shanghai, Shenzhen, Guangzhou, Qingdao, Hefei, Hangzhou, Nanjing, Chengdu, Mianyang, Fuqing, South Korea, Japan, the United States and other places with marketing positions.

Enterprise advantage

Job title category

Compensation standard

2023-an image processing algorithm engineer

Job responsibilities

1. Responsible for TV/STB/MNT and other SoC on the video image processing and display the type of circuit algorithm design and verification

2. Responsible for video image processing module of the HLS implementation and verification

3. Responsible for video image processing module of performance, power consumption, and area of analysis and optimization

4. Assist in the verification partners to improve the verification coverage

5. Assist in the completion of the FPGA validation, and FW-related validation bug inspection work

6. Assist in the completion of the IC bringup issues related to acceptance of work.

Qualifications

1. Master Degree or above, microelectronics, integrated circuits, communications and other related professionals;

2. Familiar with the video/image processing related algorithms ( noise reduction,color engineering, super-sub, compression, and other Signal Processing Engineering); and

3. Familiar with development based on deep learning algorithms for computer vision and image processing;

4. Familiar with deep learning experience supervised learning, unsupervised learning, or reinforcement learning; and

5. Deep learning framework experience (Caffe, TensorFlow, or PyTorch); and

6. Learn Matlab, C++/C , Python, DirectX, and other commonly used languages;

7. Have image/video algorithm development experience, keen, Quick Response, good logical analysis skills;

8. Active and strong, responsible, work carefully, the good team cooperation spirit.

• Number of vacancies: several

• Work location: Zhejiang-Jiaxing-Haining

• Salary range: negotiable

2023-digital IC design engineer

Job responsibilities

1. Responsible for TV/STB/MNT and other SoC on the DPU subsystem design;

2. According to product specifications, to complete the DPU Subsystem architecture design, circuit design and verification;

3. Complete the DPU subsystem, and each module of the front-end design of the check, including the DC/Formality/STA/Power, etc. checks;

4. Participation of related IP integration and integration as well as the front end of the design process;

5. Assist in the verification partners to improve the verification of coverage;

6. Assist in the completion of the FPGA validation, and FW verification of the bug convergence works;

7. Assist in the completion of the IC bringup issues related to the convergence of work;

8. Responsible for video image processing module of performance, power consumption, and area of analysis and optimization;

9. With back-end engineers to complete the layout.

Qualifications

1. Master Degree or above, microelectronics, integrated circuits, communications and other related professionals;

2. Familiarity with verilog and generally IC design flow, FPGA verification process;

3. Familiar with image processing module, including but not limited to HDR/NR/De-interlace/Contrast/Sharpness/Scaler/MEMC/Color/Gamma, and have the relevant IP design experience is preferred;

4. Active and strong, responsible, work carefully, the good team cooperation spirit.

• Number of vacancies: several

• Work location: Zhejiang-Jiaxing-Haining

• Salary range: negotiable